What is Boundary Scan | JTEG standard IEEE 1149.1
This page covers Boundary scan basics and mentions its merits over functional, structural tests, Bed of nails, multi-layer boards. It mentions boundary scan register, boundary scan JTEG standard IEEE 1149.1 and JTEG applications.
The boundary scan overcome following drawbacks of previous test methods.
• In functional test, it is difficult to replicate complete test setup to cover the end application.
• Structural test perform testing on individual partition rather than testing as a whole . It is difficult to have access to internal nodes here.
• Structure such as bed of nails is costly to fabricate and difficult to make solid connections when there are many points to access simultaneously.
• Above methods further become more complex in high density circuits comprising multiple layer boards.
As shown in the figure-1 instead of relying on mechanical connections for access, boundary scan will add dedicated test circuitry to system ICs using special registers instead of I/O pins.
Boundary Scan Register
• Boundary scan registers observe data on I/O pins.
• They can be used to override drive signals to provide test stimulus to the circuits.
• In order to have access to these registers, there is a separate serial data chain independant of functional path. The test setup information is fed to the input of the chain from SERIAL IN and this is propagated to the chain output SERIAL OUT. If there are multiple ICs they are concatenated as shown in the figure-1.
Four operations are performed by the boundary scan register.
• Transparent: Allows data to be passed through registers without modifications. This is the state of circuit during normal functioning.
• Capture: This operations captures data coming into the registers and check their values without altering it.
• Update: This operation updates outputs of the register. This is applied to the data coming into the registers. This is the way stimulus is applied to the circuit under test.
• Serial Shift: This operation executes serial shift. It enables test access to each register. It shifts test response from boundary of a register to a output register. It allows you to be scanned in comparison to the expected response. Hence it is known as boundary scan.
The boundary scan requires good co-ordination between test group, design team, suppliers and boundary scan automation software teams. In order to facilitate communication between these groups a standard known as Joint Test Access Group, IEEE 1149.1 has been developed. It is also JTEG. There are many devices manufactured with JTEG boundary scan as built-in feature.
It is considered to be efficient method to verify electrical connections between IC pins and PCB. The application is expanded to MCMs (Multi Chip Modules) and stacked-die. With built-in self tests, JTEG verifies internal memory as well as other logics. It can also be applied to system level testing. JTEG has become prefered method for field testing as it allows testing without dis-assembling the circuit. It is also used for design debugging.
Boundary Scan JTEG Signals
The figure-3 depicts boundary scan architecture with JTEG signals.
All these signals have their specific functions in the architecture.
These pins are collectively known as TAP (Test Access Port).
• TDI-Test Data In
• TCK-Test Clock
• TMS-Test Mode Select
• TDO-Test Data Out
• TRST-Test Reset
Advantages of Boundary Scan
• It avoids use of test points on the board under test as used in in circuit testing with bed of nails fixture.
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